Analog front end circuit

ABSTRACT

The present invention relates to an analog front end circuit which is preferably used for taking out an image signal from a charge coupled device, that is used as image pickup means in an electronic camera such as an electronic still camera, a video camera and the like. In the present invention, an image analog signal which is produced by, for example, the charge coupled device (CCD: not shown) is supplied to a correlated double sampling circuit (CDS)  2  through an input terminal  1.  The image analog signal is taken out through the CDS 2,  and the signal taken out from the CDS 2  is supplied to an analog type programmable gain control amplifier (PGA)  4  through a changeover switch  3.  Either the gain controlled signal by the analog PGA  4  or the signal sent from the changeover switch  3  is selected by a changeover switch  5.  The selected signal is further supplied to, for example, a 12-bit analog digital converter (ADC)  6.  The converted digital signal is supplied to a digital type programmable gain control amplifier (PGA)  7  comprised of, for example, a multiplier and is then taken out from an output terminal  8.  In this manner, the noise generation and power consumption under occasional use conditions can be minimized.

TECHNICAL FIELD

[0001] The present invention relates to an analog front end circuitwhich is preferably used when an image signal is taken out from a chargecoupled device used as image pickup means in an electronic cameraapparatus such as an electronic still camera or a video camera.Particularly, the invention concerns an analog front end circuit whichis so arranged as to enable a manner of performing gain control when theimage signal is taken out to be arbitrarily changed over according touse conditions.

BACKGROUND ART

[0002] With an analog front end circuit which is used when the imagesignal is taken out from a charge coupled device serving as image pickupmeans in an electronic camera apparatus such as an electronic stillcamera or a video camera, a plurality of gain control methods such asthose shown in FIGS. 3A to 3C have hitherto been performed.

[0003]FIG. 3A is a block diagram of an analog amplifier type analogfront end circuit which performs a first method. In this circuit of FIG.3A, an image analog signal which is produced by, for example, a chargecoupled device (hereinafter abbreviated as “CCD”: not shown) is suppliedto a correlated double sampling circuit (hereinafter abbreviated as“CDS”) 31 through an input terminal 30. The image analog signal is takenout through the CDS 31.

[0004] The signal which is taken out through the CDS 31 is supplied toan analog type programmable gain-control amplifier (hereinafterabbreviated as “the PGA”) 32. To this analog PGA 32 is further supplieda gain control signal from a control circuit 33. The signal which isamplified according to the gain control signal is supplied to an analogdigital converter (hereinafter abbreviated as “ADC”) 34, and theconverted digital signal is taken out from an output terminal 35.

[0005] In other words, this circuit of FIG. 3A is such that the analogPGA 32 performs the entire gain control as required. In order that thiscircuit provides a sufficient image quality for consumer use, the wordlength required for the ADC 34 is about 10 to 12 bits, so that a shortword length is available for the ADC 34. Therefore, the circuit of lowprice can generally be used for the ADC 34 a, and the less powerconsumption will also be achieved. Furthermore, the equivalent wordlength at the output end always corresponds with the word length of theADC 34, and the noise level at the time of high gain is the lowest.

[0006] However, when the analog PGA 32 in the circuit, controls theentire gain range as required, the power consumption by the analog PGA32 increases and hence the power consumption in the entire circuit alsoincreases. Moreover, the analog PGA 32 is difficult to make linear ofits gain control characteristic. Therefore, in order to obtain thelinear characteristic, it becomes necessary to provide a conversiontable, etc. on the relevant control software. As described above, thecircuit of FIG. 3A involves such problems as the power consumption andthe linearity of gain control.

[0007] In contrast, FIG. 3B is a block diagram of a digital amplifiertype analog front end circuit which uses a second method. It is notedthat, in that figure, the elements corresponding to those of FIG. 3A aredenoted by like reference symbols. In this circuit of FIG. 3B, thesignal which is taken out through the CDS 31 is supplied directly to theADC 36. Then, the digital signal thus converted is multiplied by a gaincontrol signal from the control circuit 33, which is performed by adigital type programmable gain control amplifier (PGA) 37.

[0008] Accordingly, in this circuit of FIG. 3B, the entire gain controlas required is performed by the digital PGA 37. Because this circuitemploys no analog PGA, the circuit structure is simple. In addition,there are less problems caused by the dispersion of circuits such as theoffset, so that the operation becomes stable. Further, it is possible tomake linear of the gain control characteristic of the digital PGA 37. Asa result, providing the conversion table, etc. on the control softwarefor obtaining the linearity can be made unnecessary.

[0009] However, in this circuit, the equivalent word length at theoutput end, etc. becomes smaller in inverse proportion to the gain whichis the multiplication in the digital PGA 37. For this reason, in orderto ensure the equivalent word length the maximum gain, it is necessaryto make the word length of the ADC 36 long. Incidentally, the wordlength which is necessary for the ADC 36 to obtain a sufficient imagequality for consumer use is about 14 bits. Accordingly, the ADC 36having such a long word length will be large in circuit scale and alsothe power consumption thereof increases extremely.

[0010] Further, in the structure, for example, which omits apre-amplifier for matching the output of the CCD with the input fullscale of the ADC 36, in order to avoid the increase in the powerconsumption, if the maximum output level of the CCD in use is low, itwill result that not all the input range of the ADC 36 are used.Therefore, the equivalent word length at the output end, etc. isreduced, which will result in a disadvantage in terms of image qualitymoreover, at the time of high gain, because all noises in the circuitsthat precede the digital PGA 37 are amplified, noises at high gain aredisadvantageous.

[0011]FIG. 3C is a block diagram of a hybrid amplifier type analog frontend circuit in which the analog and digital PGAs are mixed together toperform a third method. In this figure, the elements corresponding tothose of FIG. 3A are denoted by like reference symbols. In this circuitof FIG. 3C, the signal which is taken out through the CDS 31 is suppliedto the ADC 39 through an analog PGA 38, and the converted digital signalis supplied to the digital PGA 40. The gain control in these PGAs 38 and40 are performed by the control circuit 33.

[0012] Accordingly, in this circuit of FIG. 3C, because theamplification is also performed by the digital PGA 40 as well, the gainof the analog PGA 38 can be made smaller than in the case of the circuitof FIG. 3A and thus the power consumption can be reduced. Also, becausethe amplification is performed in the analog PGA 38, the word length ofthe ADC 39 can be made shorter than in the case of the circuit of FIG.3B. Note that the word length necessary for the ADC 39 in order toobtain a sufficient image quality for consumer use is about 12 bits.Therefore, the circuit which is cheap and of less power consumption canbe employed for the ADC 39.

[0013] However, although this circuit of FIG. 3C is superior to thecircuit of FIG. 3B in the noise at high gain but inferior to the circuitof FIG. 3A. The entire power consumption of the circuit of FIG. 3C islarger than that in the case where for example, the word length of theADC 36 is made to be 12 bits in the circuit of FIG. 3B. In addition,problems of the instability of operation and the like due to interposingthe analog PGA 38 still remain to exist as in the circuit of FIG. 3A. Onthe other hand, for example, in an electronic camera apparatus, thereare cases where the increase in noise and the increase in the powerconsumption may be permitted depending on the use conditions.

DISCLOSURE OF INVENTION

[0014] The present invention is directed to enable the circuit to beswitched over according to the use conditions and thereby enable thegeneration of noise and the power consumption to be made minimum underthose occasional use conditions. For this purpose, the present inventioncomprises both the analog amplifier and the digital amplifier andenables them to be switched over as needed for use. In connection withthat, an analog front end circuit according to the present inventionwill be disclosed below.

BRIEF DESCRIPTION OF DRAWINGS

[0015]FIG. 1 is a structure diagram showing an embodiment of an analogfront end circuit according to the present invention.

[0016]FIG. 2 is a diagram for explaining the operation thereof.

[0017]FIGS. 3A to 3C are structure diagrams showing conventional analogfront end circuits.

BEST MODE FOR CARRYING OUT THE INVENTION

[0018] In the following, the present invention will be described withreference to the drawings, FIG. 1 of which is a block diagram showingthe structure of an embodiment of an analog front end circuit accordingto the present invention.

[0019] Referring to FIG. 1, for example, an image analog signal which isproduced by a charge coupled device (CCD: not shown) is supplied to acorrelated double sampling circuit (CDS) 2 through an input terminal 1.The image analog signal is taken out through the CDS 2, and the signalwhich is taken out through the CDS 2 is supplied to an analog typeprogrammable gain control amplifier (PGA) 4 through a changeover switch3.

[0020] Either the signal which is gain-controlled by the analog PGA 4 orthe signal from the changeover switch 3 is selected by a changeoverswitch 5. The selected signal is further supplied, to, for example, a12-bit analog digital converter (ADC) 6. The converted digital signal isthen taken out from an output terminal 8 through a digital typeprogrammable gain-control amplifier (PGA) 7, for example, which iscomprised of a multiplier.

[0021] A PGA mode control circuit 9 is further provided. A signal issupplied from the PGA mode control circuit 9 to a gain control circuit10, whereby the digital PGA 7 performs gain control. Simultaneously, acontrol signal from the gain control circuit 10 is also supplied to theanalog PGA 4 through a gain conversion table 11. It is noted thatbecause the gain control responses to the control signal are differentbetween the analog PGA 4 and the digital PGA 7, the control signal isconverted using the gain conversion table 11 so that both thoseresponses may be equal.

[0022] Specifically, for example, the control signal is output from thegain control circuit 10 to the digital PGA 7 so that a predeterminedgain control response may be obtained. On the contrary, if the controlsignal is supplied to the analog PGA 4 as it is, the control responsewill be, for example, such one as indicated by a broken line a in FIG.2. Thus, when the conversion table 11 which contains such a conversioncharacteristic as indicated by-a solid line b in FIG. 2 is provided, theanalog PGA 4 will also make the same control response as that of thedigital PGA 7.

[0023] The PGA mode control circuit 9 has the following three operationmodes. In a first operation mode, the amplification up to apredetermined gain is performed by the analog PGA 4 and theamplification thereafter is performed by the digital PGA 7. In a secondoperation mode, the gain of the analog PGA 4 is fixed and theamplification to the desired gain is performed by the digital PGA 7 in athird operation mode, the operation of the analog PGA 4 is stopped andthe entire gain amplification is performed only by the digital PGA 7. Byswitching over those operation modes, the desired gain control isperformed.

[0024] Specifically, when the gain is gradually increased, given thatthe maximum gain is, e.g. 36 dB, the analog PGA 4 is the gain controlfor 0 to 18 dB in the first operation mode. After the gain of the analogPGA 4 has reached 18 dB, the digital PGA 7 performs the gain control for0 to 18 dB. In the second operation mode, for example, the analog PGA 4is controlled for fixed the gain at an arbitrary value and the digitalPGA 7 is controlled for the gain control for 0 to 36 dB.

[0025] Further, in the third operation mode, the operation of the analogPGA 4 is stopped, and the digital PGA 7 is controlled for the gain for 0to 36 dB. In this connection, the PGA mode control circuit 9 furthersupplies a control signal to a power supply control circuit 12. Thepower supply control circuit 12 controls the power supply of the analogPGA 4. Also, by a control signal from the PGA mode control circuit 9,the changeover switches 3, 5 are activated for the selection of signal,whereby the operation of the analog PGA 4 is stopped.

[0026] It is noted that, the control signal from the PGA mode controlcircuit 9 for changing over the operation mode or for controlling thegain to be controlled is supplied as a data signal from the outside (notshown) through, for example, a data signal terminal 13. Additionally,the format of the data signal supplied through the data input terminal13 may be of any type if only it is available for the above-describedPGA mode control circuit 9. For example, there can be used a format ofdata signal which is common to the above-described analog front endcircuit and the other circuits.

[0027] In a case where, for example, it is desired to reduce the powerconsumption in the above-described circuit as much as possible, it ispreferable to make the operation mode to be the above-described thirdoperation mode i.e. the full-digital mode. By doing so, it is possibleto greatly reduce the power consumption by stopping the operation of theanalog PGA 4. On the other hand when the reduction of noise is intended,it is preferable to make the operation mode which is the above-describedfirst operation mode i.e. the hybrid mode. By doing so, it is possibleto less the amplified gain by the digital PGA 7 and thereby suppress theamplification of noise generated in the preceding circuits.

[0028] Further, in the above-described second operation mode, in whichis the digital mode with a pre-amplifier (fixed gain), the power isconsumed as much as in the hybrid mode or the first operation mode,whereas more noise is generated than in the hybrid mode. However, inthis second operation mode, because gain of the analog PGA 4 in use isunchanged, there will occur no inconvenience such as the transientphenomena due to the offset just as in the third operation mode, or thefull-digital mode. Therefore, the satisfactory gain control can beperformed.

[0029] On that account, when the above-described circuit is used in anelectronic still camera, because noise generation is permitted, in amonitor mode in which a picked-up image is only displayed in the finder,the operation mode is made to be the full-digital mode in which thepower consumption is the minimum. At the time of capturing or recordingpicked-up still images, the operation mode is made to be the hybrid modein which the noise generation is the least. Additionally, the timerequired for the capturing is short and the operation mode after thecapturing is returned again to the full-digital mode.

[0030] Also, when a moving image is picked up and recorded, theoperation mode is made to enter the digital mode with a preamplifier, inwhich the noise generation is relatively small and there occurs noinconvenience such as transient phenomena. It is noted that, in case ofthe moving image, irregular noise, etc. generated in the circuit are notoutstanding and some noise are permissible. By changing over theoperation mode depending on the occasional use conditions or the like inthis manner, it is possible to reduce the entire power consumption andalso suppress the generation of noise to a tolerable extent.

[0031] Accordingly, because it is arranged, in this embodiment, thatboth the analog amplifier and digital amplifier are provided, and theyare allowed to be switched over for use as needed, it is possible tochange over the circuit according to the occasional use conditions, andthereby minimize the noise generation and the power consumption underthose occasional use conditions. Therefore, according to the presentinvention, it is possible to overcome the problems of minimizing thenoise generation and the power consumption which could not be solved bythe conventional apparatus.

[0032] Additionally, because the above-described embodiment is providedwith the gain conversion table 11, it is possible to control both of theanalog PGA 4 and the digital PGA 7 by a single control signal forexample. This eliminates the necessity of providing a conversion tablefor obtaining, e.g. a linear characteristic on a control software, thusallowing the entire gain control to be performed by a simple controlsignal. Further, such a gain conversion table can also be provided inthe control system of the PGA 7. Alternatively, the table can also beprovided in the both systems of control so as to control the PGA 4 andthe PGA 7.

[0033] Moreover, the above-described embodiment has the third operationmode in which the changeover switches 3, 5 provided in front of andbehind the analog PGA 4 is activated to make the analog PGA 4 bypassedand a control signal is supplied to the power supply control circuit 12to make the power supply of the analog PGA 4 stopped. Therefore, in thethird operation mode, or the full-digital mode, it is possible to makethe power consumption at the analog PGA 4 completely null and therebyminimize the entire power consumption.

[0034] Furthermore, the above-described circuit can be unified togetherwith a correlated double sampling circuit (CDS) into an integratedcircuit. By doing so, it is possible to form an extremely efficientanalog front end circuit which enables the operation mode to bearbitrarily changed over according to the occasional use conditions.Consequently, the analog front end circuit which is adapted for suchoccasional use conditions that stress is placed upon the reduction inthe power consumption, or stress is placed upon obtaining a low-noiseimage signal, etc. can be realized as a single integrated circuit.

[0035] As described above, the analog front end circuit comprises: theanalog amplifier which receives the analog signal and the gain of whichis controllable; the analog digital converter which digitizes the outputof the analog amplifier; and the digital amplifier which multiplies theoutput of the analog digital converter by an arbitrary value; wherein,in the first operation mode, the amplification to a predetermined gainis performed by the analog amplifier; in the amplification thereafter isperformed by the digital amplifier; in the second operation mode, thegain of the analog amplifier is fixed and the amplification up to adesired gain is performed by the digital amplifier, and the thirdoperation mode in which the operation of the analog amplifier is stoppedand the amplification for the entire gain is performed only by thedigital amplifier; and the desired signal processing is performed byswitching over the operation mode among the first to the third operationmodes. Therefore, by switching over the circuit according to the useconditions, the noise generation and the power consumption under thoseoccasional use conditions can be minimized.

[0036] It is noted that the present invention is not limited to theabove-mentioned embodiment, but various modifications are possiblewithout departing from the spirit of the present invention.

[0037] In short, according to the present invention, because it isarranged that both the analog amplifier and the digital amplifier areprovided and those amplifiers can be switched over for use as needed, bychanging over the circuit according to the occasional use conditions, itis possible to minimize the noise generation and the power consumptionunder those occasional use conditions.

[0038] Moreover, according to the present invention, performing the gaincontrol of the analog and digital amplifiers by a single control signaland by providing the signal conversion table in one of the gain controlsystems for the analog and digital amplifiers makes it unnecessary toprovide a conversion table for obtaining, e.g. a linear characteristicon a control software. Therefore, it becomes possible to perform theoverall gain control by a simple control signal.

[0039] Furthermore, according to the invention, a bypass line isprovided via the changeover switches in front of and behind the analogamplifier, and in the third operation mode, the analog amplifier isbypassed and at the same time the power supply of the analog amplifieris cut off by activating over the changeover switches. Thus, in thefull-digital mode which is the third operation mode, it is possible tomake the power consumption of the analog amplifier completely null andthe entire power consumption can be minimized.

[0040] In addition, according to the present invention, because theanalog amplifier, analog digital converter and digital amplifier areunified into an integrated circuit including the correlated doublesampling circuit for taking out the image signal from the charge coupleddevice, an analog front end circuit which is adapted for such occasionaluse conditions that stress is placed upon the reduction in the powerconsumption, or stress is placed upon obtaining low-noise image signalscan be realized as a single integrated circuit.

[0041] Consequently, according to the present invention, it is possibleto easily overcome those problems of minimizing the noise generation andthe power consumption which could not be solved by the conventionalapparatus.

DESCRIPTION OF REFERENCE NUMERALS

[0042]1 . . . INPUT TERMINAL

[0043]2 . . . CORRELATED DOUBLE SAMPLING CIRCUIT (CDS)

[0044]3, 5 . . . CHANGEOVER SWITCHES

[0045]4 . . . ANALOG TYPE PROGRAMMABLE GAIN CONTROL AMPLIFIER (ANALOGPGA)

[0046]6 . . . ANALOG DIGITAL CONVERTER (ADC)

[0047]7 . . . DIGITAL TYPE PROGRAMMABLE GAIN CONTROL AMPLIFIER (DIGITALPGA)

[0048]8 . . . OUTPUT TERMINAL

[0049]9 . . . PGA MODE CONTROL CIRCUIT

[0050]10 . . . GAIN CONTROL CIRCUIT

[0051]11 . . . GAIN CONVERSION TABLE

[0052]12 . . . POWER SUPPLY CONTROL CIRCUIT

[0053]13 . . . DATA INPUT TERMINAL

[0054]30 . . . INPUT TERMINAL

[0055]31 . . . CORRELATED DOUBLE SAMPLING CIRCUIT (CDS)

[0056]32, 38 . . . ANALOG TYPE PROGRAMMABLE GAIN CONTROL AMPLIFIER(ANALOG PGA)

[0057]33 . . . CONTROL CIRCUIT

[0058]34, 36, 39 . . . ANALOG DIGITAL CONVERTERS (ADC)

[0059]35 . . . OUTPUT TERMINAL

[0060]37, 40 . . . DIGITAL TYPE PROGRAMMABLE GAIN CONTROL AMPLIFIER(DIGITAL PGA)

1. An analog front end circuit comprising: an analog amplifier which receives an analog signal and the gain of which is controllable; an analog digital converter which digitizes the output of the analog amplifier; and a digital amplifier which multiplies the output of the analog digital converter by an arbitrary value, wherein in a first operation mode, the amplification up to a predetermined gain is performed by said analog amplifier and the amplification thereafter is performed by said digital amplifier; and in a second operation mode, the gain of said analog amplifier is fixed and the amplification to a desired gain is performed by said digital amplifier; in a third operation mode, the operation of said analog amplifier is stopped and the amplification for the entire gain is performed only by said digital amplifier, and said operation mode is switched over among said first to third operation modes, to perform desired signal processing.
 2. An analog front end circuit according to claim 1, wherein the gain controls of said analog amplifier and said digital amplifier are performed by a single control signal; and a signal conversion table is provided in one or both of the gain control systems of said analog amplifier and said digital amplifier.
 3. An analog front end circuit according to claim 1, wherein a bypass line is provided via changeover switches provided in front of and behind said analog amplifier; and in said third operation mode, by activating the changeover switches, said analog amplifier is bypassed and a power supply of said analog amplifier is cut off.
 4. An analog front end circuit according to claim 1, wherein said analog amplifier, said analog digital converter, and said digital amplifier are unified into an integrated circuit including a correlated double sampling circuit for taking out an image signal from a charge coupled device. 